FIG. 1 shows a basic structure of a color liquid crystal display using an active matrix substrate. In FIG. 1, on the surface of a substrate 10 are gate lines G0, G1, G2, . . . running in the X direction, source lines S1, S2, S3, . . . running in the Y direction, a plurality of pixel electrodes 12 placed in the positions corresponding to the intersections of the source lines S1, S2, S3, . . . and the gate lines G1, G2, G3, . . . , and a thin film transistor 11 (hereinafter "TFT") connected with each of the pixel electrodes.
In a selection period, that is, a period in which the TFT 11 is on by the signals from the gate lines G1, G2, G3, . . . , the picture signals provided by the source lines S1, S2, S3, . . . are written in a liquid-crystal-capacitance portion CLC consisting of a common electrode 26 formed on an opposite substrate 20, a pixel electrode 12, and liquid crystal 30 encapsulated between the electrodes 26 and 12. In a non-selection period, that is, a period in which the TFT 11 is off, the picture signals written in the liquid-crystal-capacitance portion CLC in the selection period are retained.
Note that in order to achieve a high-quality display, the storage characteristics in the non-selection period need to be good. For that purpose, it will be effective to set up a storage capacitor CS electrically parallel to the liquid-crystal-capacitance portion CLC. As to the storage capacitor CS, it has been proposed that the storage capacitor CS be established between the adjacent gate line and the pixel electrode 12, or that the storage capacitor CS be established between a storage line (not shown in FIG. 1) separately formed and the pixel electrode 12.
The storage capacitor CS formed as was described above, the pixel electrode 12, the TFT 11, and other accompanying wirings and others constitute pixel regions P11, P12, P13 . . . Note that although in FIG. 1 there is no pixel region between the pixel region P11 and a pixel region P31, there can be a pixel region for blue or a dummy pixel region in the area in question.
The opposite substrate 20 has a color filter 21. The color filter 21 generally consists of a red filter R, a green filter G and a blue filter B. A set of the red filter R, the green filter G and the blue filter B as one unit is repeatedly placed in the display area. As the arrangements of the color filter 21, there are a stripe arrangement, a mosaic arrangement or a delta arrangement. FIG. 12 shows a color arrangement pattern according to the delta arrangement, and FIG. 13 shows an example of a color arrangement pattern according to the mosaic arrangement. The delta arrangement or the mosaic arrangement is more advantageous than the stripe arrangement in that a more delicate picture can be obtained than according to the stripe arrangement because each of the color elements is dispersed uniformly in the display area.
FIG. 3A of Japanese Patent Publication No. TOKUKOUHEI 3-64046 and others disclose a liquid crystal display making use of the delta arrangement, and FIGS. 8C to 8F of the same publication and others disclose a liquid crystal display making use of the mosaic arrangement.
In the liquid crystal display using the delta arrangement disclosed in the above-mentioned publication, as shown in FIG. 14, a set of three pixel regions P21, P22, and P23 corresponding to the red filter R, the green filter G, and the blue filter B as one unit is placed periodically in the X direction. Note that the pixel regions P21, P22, and P23 in a pixel array at an even-numbered line are displaced from the pixel regions P11, P12, and P13 or the pixel regions P31, P32, and P33 in a pixel array at an odd-numbered line by a distance corresponding to a 1/2 period of the above-mentioned one unit. Accordingly, between the pixel array at an odd-numbered line and that at an even-numbered line, the center of the pixel regions P11, P12, P13, . . . are displaced right and left by 1.5 pixel pitches.
The pixel region P21 will be explained as an example, because each of the pixel regions has the same basic structure. In the pixel region P21, a source region 111 of the TFT 11 is connected with a source line S1, a gate electrode 113 is connected with a gate line G2, and a drain region 112 is connected with a pixel electrode 12.
In the pixel region P21, a first electrode C1 electrically connected with the drain region 112 of the TFT 11 and the pixel electrode 12, and a second electrode C2 projecting in the Y direction from a adjacent gate line G1 are formed. The first electrode C1 is usually made of a doped silicon film. The first electrode C1 and the second electrode C2 are, as described below, opposed across a dielectric film. The storage capacitor CS is formed as described above between the pixel electrode 12 and the adjacent gate line G1.
Since each of the source lines S1, S2, S3, . . . extends with a crank-like shape in the Y direction, and does not require a complicated color changeover circuit to supply a plurality of color signals with the same source line at appropriate timing, only the pixel electrode 12 in the pixel region corresponding to the same color is connected with the same source line through the TFT 11. Accordingly, the same source line has the pixel regions corresponding to the same color alternately on both sides of the source line at each line. The source line S2, for instance, has pixel regions P12, P22, P32, . . . corresponding to green alternately on both sides of the source line S2. And necessarily, the position of the TFT 11 and the source line is reversed at each line.
As a result, while as to the pixel regions P11, P12, P13, . . . in the X direction along the gate lines G1, G2, G3, . . . , the relative position of the TFT 11, the pixel electrode 12 and the storage capacitor CS (the first electrode C1 and the second electrode C2) is the same, as to the pixel regions P12, P22, P32, . . . in the Y direction along the source line S2, the relative position of the TFT 11, the pixel electrode 12 and the storage capacitor CS is symmetrical horizontally at every line. For example, comparing the pixel regions P11, P12, P13, . . . connected with the gate line G1 with the pixel regions P21, P22, P23, . . . connected with the gate line G2, the relative position of the TFT 11, the pixel electrode 12 and the storage capacitor CS is symmetrical horizontally.
The manufacturing method of the active matrix substrate with the above-mentioned structure will be briefly explained with reference to FIG. 15. FIGS. 15(A), (B) and (C) are a I-I' sectional view, a II-II' sectional view, and a III-III' sectional view of FIG. 14, respectively.
In FIG. 15(A), after a polycrystalline silicon thin film is formed on the substrate 10, a polycrystalline silicon thin film 110 is formed which constitutes an active region of the TFT 11 and the first electrode C1 of the storage capacitor CS by the patterning according to photolithography.
Then a gate oxide 114 and a dielectric film C3 of the storage capacitor CS are formed by thermal oxidation of the polycrystalline silicon film 110. Next, only the polycrystalline silicon film 110 to constitute the storage capacitor CS is selectively doped to form the first electrode C1 of the storage capacitor CS.
Then a gate electrode 113 and the second electrode C2 of the storage capacitor CS are formed of a doped polycrystalline silicon film according to photolithography. At this step, in the pixel region P21, the gate electrode 113 and the gate line G2 are electrically connected, and the second electrode C2 and the adjacent gate line G1 are electrically connected.
Next, a source region 111 and a drain region 112 are formed by implanting ions with the gate electrode 113 used as a mask. And after an interlayer insulating film 115 is formed, a through-hole is made in it.
Then a source terminal 118 and a drain terminal 119 are electrically connected with the source region 111 and the drain region 112, respectively. The source terminal 118 is electrically connected with the source line S1, while the drain terminal 119 is electrically connected with the pixel electrode 12.
As was described above, the TFT 11 and the storage capacitor CS are formed in the pixel region P21, and at the same time, as shown in FIGS. 15(B) and (C), the storage capacitor CS is formed in the pixel regions P11, P12 and P22, too.
When the pattern shown in FIG. 14 is used, however, if the alignment is not obtained along the horizontal direction (in the X direction) in forming each component on the substrate 10 according to photolithography, in the pixel regions P12, P22, P32, . . . in the Y direction along the source line S2, for example, the structure parameter varies at every line.
In other words, in FIG. 16, when the overlap of a formation pattern A1 of a lower polycrystalline silicon film to form the TFT 11 and the first electrode C1 of the storage capacitor CS, and a formation pattern A2 of an upper polycrystalline silicon film to form the gate lines G1, G2, G3, . . . , the gate electrode 113 and the second electrode C2 of the storage capacitor CS is patterned with oblique lines as facing portions C0 of the storage capacitors CS, if the alignment is not obtained along the horizontal direction between the formation pattern A1 of the lower polycrystalline silicon film and the formation pattern A2 of the upper polycrystalline silicon film, the area of the facing portions C0 patterned with oblique lines varies between the storage capacitors CS (ODD) (these storage capacitors are connected with the gate lines G0, G2, . . .) of the pixel regions P11, P12, . . . P31, P32, . . . at odd-numbered lines selected by the gate lines G1, G3, . . . , and the storage capacitors CS (EVEN) (these storage capacitors are connected with the gate lines G1, G3, . . . ) of the pixel regions P21, P22, . . . selected by the gate lines G2, (G4), . . .
Since FIG. 16 shows an ideal example in which the alignment is obtained right and left, the capacitance value of the storage capacitor CS (ODD) is equal to that of the storage capacitor CS (EVEN).
If the alignment is not achieved in the horizontal direction, however, the capacitance value of the storage capacitor CS (ODD) is different from that of the storage capacitor CS (EVEN). For example, if the formation pattern A1 of the lower polycrystalline silicon thin film is displaced from the formation pattern A2 of the upper polycrystalline silicon thin film in the direction shown by an arrow R, the capacitance value of the storage capacitor CS (ODD) increases whereas that of the storage capacitor CS (EVEN) decreases.
As a result, when the N-type TFT is used, because the optimum LC common voltage of the gate lines G1, G3, . . . at odd-numbered lines is higher than that of the gate lines G2, . . . at even-numbered lines, there occurs a difference between the two optimum LC common voltages, and flickers are caused in each gate line.
In order to solve the above-mentioned problems, an object of the present invention is to provide an active matrix substrate which does not produce flickers even when the pixel electrodes in each of the pixel regions connect with the same source line alternately from right and left at every line, by improving the formation pattern of each of the electrodes constituting the storage capacitors.
Another object of the present invention is to provide a high-quality color liquid crystal display using an active matrix substrate formed as described above.